Taiwan experienced an earthquake on April 3 reaching magnitude level 7.2 (the largest in Taiwan over the past 25 years). The maximum magnitude measured at the Hsinchu, Longtan, and Zhunan science parks was 5, and reached magnitude 4 at the Taichung and Tainan science parks.

Based on TSMC's ample experience and capabilities in earthquake response and damage prevention, as well as regular disaster drills to ensure full readiness, overall tool recovery of our fabs reached more than 70% within 10 hours of the April 3 earthquake, with new fabs such as the Fab 18 facility reaching more than 80%. Thanks to the collaborative efforts of TSMC colleagues and our supplier partners, we were fully recovered by the end of the third day. At the same time, we are maintaining close contact with customers and communicating with them regarding impact as appropriate.

There were no power outages, no structural damage to our fabs, and there is no damage to our critical tools, including all of our EUV lithography tools. That being said, a certain number of wafers in process were impacted and had to be scrapped, but we expect most of the lost production to be recovered in the second quarter, and thus minimal impact to our second quarter revenue. We expect the total impact from the earthquake to reduce our second quarter gross margin by about 50 basis points, mainly due to the losses associated with wafer scraps and materials loss. TSMC maintains its full-year revenue guidance of low-to-mid-twenties percentage growth given at the January institutional investors' conference. Based on a preliminary assessment, the Company estimated related earthquake losses to be approximately NT$3 billion, net of insurance claim, and will recognize it in the second quarter of 2024.

CEA-Leti researcher Rémy Gassilloud estimated that in a single wafer process, two minutes per wafer is the maximum cost-effective process time. But two minutes is only enough time to deposit about a 2nm-thick film.

Some process adjustments can improve throughput. Silicon dioxide ALD often uses large furnaces to process many wafers at once. Plasma activation can ionize reagents and accelerate film formation. Still, Gassilloud estimates that 10nm is the maximum practical thickness for ALD films.

As ALD has become a mainstream process, the industry has found applications for it beyond core device materials, in a variety of sacrificial and spacer layers. For example, double- and quadruple-patterning schemes often use ALD for “pitch-doubling.” By depositing a spacer material on either side of a patterned “mandrel,” then removing the mandrel, the process can cut the original pitch in half without the need for an additional, more costly lithography step.⁠

...atomic layer etching (ALE) might be used to remove unwanted material. ALE operates in the same step-by-step manner as ALD. The first half of a cycle reacts with the existing surface, weakening the bond to the underlying material. Then, a second step — typically ion bombardment — removes the weakened layer. For example, in ALE etching of silicon, chlorine gas reacts with the surface to form various SiClx compounds. The chlorination process weakens the inter-silicon bonds between the surface and the bulk, and the chlorinated layer is easily sputtered away. The layer-by-layer nature of ALE depends on preferential removal of the surface material relative to the bulk (SiClx vs. Si in this case). The “ALE window” is the combination of energy and temperature at which the surface layer is completely removed without damaging the underlying material.